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TurboSFV | 
2025-11-01 13:08:26 |
| TurboSFV v10.61 - Supported SIMD instruction sets |
Notes to TurboSFV v10.61:
Following some SIMD (Single Instruction Multiple Data) implementations in previous versions of TurboSFV, in this new version there is a CPU feature list, regarding needed SIMD instruction sets for a faster calculation of checksums. Having
a deeper look at the CPU, where TurboSFV is running, a green check mark indicates that an instruction set is available and a red error sign means, that a feature isn't supported.
XMM, YMM and ZMM are the names of the needed CPU registers, where SIMD instructions do operate on: SSE (Streaming SIMD Extensions) instructions use XMM registers (128 bit), AVX2 (Advanced Vector Extensions) can use YMM registers (256 bit)
and AVX512 instructions can work with ZMM registers (512
bit).
For example, the AVX2 implementation of BLAKE3 in TurboSFV uses instructions from the CPU instruction sets SSE2, SSE4.1, AVX and AVX2, together with YMM registers. If one of the needed features isn't supported by the CPU, then the
implementation can't be used, because the application simply would crash. TurboSFV checks the needed features in advance and disables an implementation, if needed. At least an implementation based on legacy instructions can be used
then.
The SHA extension is very special, because the instructions belonging to this family aren't really SIMD instructions: They perform parts of the algorithm (SHA-1, SHA-224 or SHA-256) in one shot, which would normally need a bunch of single
basic instructions. However, they operate with XMM registers, which need to be prepared with SSE
instructions.
Instructions from the AVX512 family aren't actually used by TurboSFV, but the basic instruction set AVX512F (foundation) is already listed, together with the needed ZMM registers, for possible future extensions of TurboSFV.
Finally, the original processor name, directly picked up from special CPU registers, is also mentioned.
Feel free to add a comment regarding this new version here.
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TurboSFV
Cologne, Germany |
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