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TurboSFV | 
2025-03-01 12:08:48 |
| TurboSFV v10.40 - SHA-256 with SSE support (SHA256RNDS2) |
Notes to TurboSFV v10.40:
With this new version, the calculation of SHA-256 and SHA-224 checksums can now optionally use special SSE (Streaming SIMD Extensions) based CPU instructions, which are available as a part of the Intel SHA extensions in modern CPUs since
2016.
The SHA-256 algorithm basically works as follows: The input message, for example a file, is split into blocks with a size of 64 bytes. Every block will be processed in 64 computation rounds, each equipped with basic CPU instructions, all
rounds together quite compute-intensive. The output of this rounds is then kept in eight 32 bit state variables, which - together with the next block - represent the input for the next 64 rounds. If all input bytes are consumed, then the
eight state variables build the SHA-256 hash value. The same algorithm is used for SHA-224, with a different initial vector and a smaller output of 224 bits.
There are three SSE based instructions, which help to accelerate the computation: The instructions SHA256MSG1 and SHA256MSG2 help to consume the input bytes and to prepare them for the calculation of the eight 32 bit state variables, which
is then done by calling twice the SHA256RNDS2 instruction with changing XMM registers (128 bit), each holding four state variables. The resulting calculation speed can be up to seven times faster, if the input bytes are available with the
appropriate
speed.
The used CPU must of course provide the three SSE instructions: TurboSFV checks that before using them, along with the existence of other needed SSE enhancements up to SSE4.1. If failed, then only the legacy instructions (x86 / x86-64
(x64)) can be used. Otherwise the SSE calculation mode will be offered. Both methods produce the same hash
values.
Comments regarding this new version can be added here.
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TurboSFV
Cologne, Germany |
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